preset_5k.v
///////////////////////////////////////////////////
// PRESET_5K.V Version 1.0 //
// Example of 5k FF with Async. Preset //
// implemented with inverter on input and output //
// of FF because FFs have only async. resets //
// November 1997 //
///////////////////////////////////////////////////
module preset_5k (CLK, DATA, PRESET, Q);
input CLK, DATA, PRESET;
output Q;
reg Q;
always @ (posedge CLK or posedge PRESET)
begin: SET_FLOP
if (PRESET)
Q <= 1;
else
Q <= DATA;
end
endmodule
barrel.v
/////////////////////////////////////////
// BARREL.V Version 1.0 //
// Xilinx HDL Synthesis Design Guide //
// XAPP 26 http://www.xilinx.com //
// 16-bit Barrel Shifter [shift right] //
// May 1997 //
/////////////////////////////////////////
module barrel (S, A_P, B_P);
input [3:0] S;
input [15:0] A_P;
output [15:0] B_P;
reg [15:0] B_P;
wire [1:0] SEL1, SEL2;
reg [15:0] C;
assign SEL1 = S[1:0];
assign SEL2 = S[3:2];
always @ (A_P or SEL1)
begin
case (SEL1)
2'b00 : // Shift by 0
begin
C <= A_P;
end
2'b01 : // Shift by 1
begin
C[15] <= A_P[0];
C[14:0] <= A_P[15:1];
end
2'b10 : // Shift by 2
begin
C[15:14] <= A_P[1:0];
C[13:0] <= A_P[15:2];
end
2'b11 : // Shift by 3
begin
C[15:13] <= A_P[2:0];
C[12:0] <= A_P[15:3];
end
default :
C <= A_P;
endcase
end
always @ (C or SEL2)
begin
case (SEL2)
2'b00 : // Shift by 0
begin
B_P <= C;
end
2'b01 : // Shift by 4
begin
B_P[15:12] <= C[3:0];
B_P[11:0] <= C[15:4];
end
2'b10 : // Shift by 8
begin
B_P[7:0] <= C[15:8];
B_P[15:8] <= C[7:0];
end
2'b11 : // Shift by 12
begin
B_P[3:0] <= C[15:12];
B_P[15:4] <= C[11:0];
end
default :
B_P <= C;
endcase
end
endmodule
barrel_org.v
///////////////////////////////////////////////////
// BARREL_ORG.V Version 1.0 //
// Xilinx HDL Synthesis Design Guide //
// Unoptimized model for a 16-bit Barrel Shifter //
// THIS EXAMPLE IS FOR COMPARISON ONLY //
// Use BARREL.V //
// January 1998 //
///////////////////////////////////////////////////
module barrel_org (S, A_P, B_P);
input [3:0] S;
input [15:0] A_P;
output [15:0] B_P;
reg [15:0] B_P;
always @ (A_P or S)
begin
case (S)
4'b0000 : // Shift by 0
begin
B_P <= A_P;
end
4'b0001 : // Shift by 1
begin
B_P[15] <= A_P[0];
B_P[14:0] <= A_P[15:1];
end
4'b0010 : // Shift by 2
begin
B_P[15:14] <= A_P[1:0];
B_P[13:0] <= A_P[15:2];
end
4'b0011 : // Shift by 3
begin
B_P[15:13] <= A_P[2:0];
B_P[12:0] <= A_P[15:3];
end
4'b0100 : // Shift by 4
begin
B_P[15:12] <= A_P[3:0];
B_P[11:0] <= A_P[15:4];
end
4'b0101 : // Shift by 5
begin
B_P[15:11] <= A_P[4:0];
B_P[10:0] <= A_P[15:5];
end
4'b0110 : // Shift by 6
begin
B_P[15:10] <= A_P[5:0];
B_P[9:0] <= A_P[15:6];
end
4'b0111 : // Shift by 7
begin
B_P[15:9] <= A_P[6:0];
B_P[8:0] <= A_P[15:7];
end
4'b1000 : // Shift by 8
begin
B_P[15:8] <= A_P[7:0];
B_P[7:0] <= A_P[15:8];
end
4'b1001 : // Shift by 9
begin
B_P[15:7] <= A_P[8:0];
B_P[6:0] <= A_P[15:9];
end
4'b1010 : // Shift by 10
begin
B_P[15:6] <= A_P[9:0];
B_P[5:0] <= A_P[15:10];
end
4'b1011 : // Shift by 11
begin
B_P[15:5] <= A_P[10:0];
B_P[4:0] <= A_P[15:11];
end
4'b1100 : // Shift by 12
begin
B_P[15:4] <= A_P[11:0];
B_P[3:0] <= A_P[15:12];
end
4'b1101 : // Shift by 13
begin
B_P[15:3] <= A_P[12:0];
B_P[2:0] <= A_P[15:13];
end
4'b1110 : // Shift by 14
begin
B_P[15:2] <= A_P[13:0];
B_P[1:0] <= A_P[15:14];
end
4'b1111 : // Shift by 15
begin
B_P[15:1] <= A_P[14:0];
B_P[0] <= A_P[15];
end
default :
B_P <= A_P;
endcase
end
endmodulebidir_io_from_lb.v
// Xilinx Verilog produced by program ngd2ver, Version M1.3.7
// Date: Mon Sep 8 17:10:12 1997
// Design file: /var/tmp/bidir_io_from_lb.ngd
// Device: xc4000ex
`timescale 1 ns/1 ps
module bidir_io_from_lb (OE, IGATE, P, O, IQ);
input OE;
input IGATE;
inout [1:0] P;
input [1:0] O;
output [1:0] IQ;
wire INV_FF_I0_OUT, INV_FF_I1_OUT, 'FF_I0/D_BUF , 'FF_I0/G_INV ,
'FF_I1/D_BUF , 'FF_I1/G_INV , TRI_0_2_INV, TRI_1_2_INV, GND;
`ifdef GSR_SIGNAL
wire GSR = `GSR_SIGNAL ;
`else
wire GSR ;
`endif
X_INV INV_FF_I0 (.IN (IGATE), .OUT (INV_FF_I0_OUT));
X_INV INV_FF_I1 (.IN (IGATE), .OUT (INV_FF_I1_OUT));
X_TRI TRI_0 (.IN (O[0]), .OUT (P[0]), .CTL (TRI_0_2_INV));
X_TRI TRI_1 (.IN (O[1]), .OUT (P[1]), .CTL (TRI_1_2_INV));
X_BUF 'FF_I0/D_BUF_2 (.IN (P[0]), .OUT ('FF_I0/D_BUF ));
X_INV 'FF_I0/G_INV_3 (.IN (INV_FF_I0_OUT), .OUT ('FF_I0/G_INV ));
X_LATCH 'FF_I0/INLATCH (.IN ('FF_I0/D_BUF ), .CLK ('FF_I0/G_INV ), .SET (GND), .RST (GSR), .OUT (IQ[0]));
X_BUF 'FF_I1/D_BUF_7 (.IN (P[1]), .OUT ('FF_I1/D_BUF ));
X_INV 'FF_I1/G_INV_8 (.IN (INV_FF_I1_OUT), .OUT ('FF_I1/G_INV ));
X_LATCH 'FF_I1/INLATCH (.IN ('FF_I1/D_BUF ), .CLK ('FF_I1/G_INV ),
.SET (GND), .RST (GSR), .OUT (IQ[1]));
X_INV TRI_0_2_INV_13 (.IN (OE), .OUT (TRI_0_2_INV));
X_INV TRI_1_2_INV_14 (.IN (OE), .OUT (TRI_1_2_INV));
X_ZERO GND_15 (.OUT (GND));
X_PD NGD2VER_PD_10 (.OUT (GSR) );
endmodule
bidir_logiblox.v
///////////////////////////////////////////
// BIDIR_LOGIBLOX.V Version 1.0 //
// This is an example of using LogiBLOX //
// to create a bi-directional port. //
// August 1997 //
///////////////////////////////////////////
//----------------------------------------------------
// LogiBLOX BIDI Module "bidir_io_from_lb"
// Created by LogiBLOX version M1.3.7
// on Mon Sep 8 17:10:15 1997
// Attributes
// MODTYPE = BIDI
// BUS_WIDTH = 2
// IN_TYPE = LATCH
// OUT_TYPE = TRI
//----------------------------------------------------
module bidir_logiblox (DATA, READ_WRITE);
input READ_WRITE ;
inout [1:0] DATA ;
reg [1:0] LATCH_OUT ;
wire [1:0] DATA_OUT ;
assign DATA_OUT[0] = LATCH_OUT[0] & LATCH_OUT[1];
assign DATA_OUT[1] = LATCH_OUT[0] | LATCH_OUT[1];
// LogBLOX instantiation
bidir_io_from_lb BIDIR_BUSSED_PORT
( .O(DATA_OUT), .OE(READ_WRITE), .P(DATA),
.IQ(LATCH_OUT), .IGATE(READ_WRITE));
endmodule
module bidir_io_from_lb(O, OE, P, IQ, IGATE);
input [1:0] O;
input OE;
input IGATE;
inout [1:0] P;
output [1:0] IQ;
endmodule
bidir_infer.v ////////////////////////////////////////////////////////////////////
// BIDIR_INFER.V Version 1.0 //
// This is an example of an inference of a bi-directional signal. //
// Note: Logic description of port should always be on top-level //
// code when using Synopsys Compiler and verilog. //
// August 1997 //
////////////////////////////////////////////////////////////////////
module bidir_infer (DATA, READ_WRITE);
input READ_WRITE ;
inout [1:0] DATA ;
reg [1:0] LATCH_OUT ;
always @ (READ_WRITE)
begin
if (READ_WRITE == 1'b1)
LATCH_OUT <= DATA;
end
assign DATA[0] = READ_WRITE ? 1'bZ : (LATCH_OUT[0] & LATCH_OUT[1]);
assign DATA[1] = READ_WRITE ? 1'bZ : (LATCH_OUT[0] | LATCH_OUT[1]);
endmodule
bidir_instantiate.v ////////////////////////////////////////////
// BIDIR_INSTANTIATE.V Version 1.0 //
// This is an example of an instnatiation //
// of a bi-directional port. //
// August 1997 //
////////////////////////////////////////////
module bidir_instantiate (DATA, READ_WRITE);
input READ_WRITE ;
inout [1:0] DATA ;
reg [1:0] LATCH_OUT ;
wire [1:0] DATA_OUT ;
wire GATE ;
assign GATE = ~READ_WRITE;
assign DATA_OUT[0] = LATCH_OUT[0] & LATCH_OUT[1];
assign DATA_OUT[1] = LATCH_OUT[0] | LATCH_OUT[1];
// I/O primitive instantiation
ILD_1 INPUT_PATH_0 (.Q(LATCH_OUT[0]), .D(DATA[0]), .G(GATE));
ILD_1 INPUT_PATH_1 (.Q(LATCH_OUT[1]), .D(DATA[1]), .G(GATE));
OBUFT_S OUPUT_PATH_0 (.O(DATA[0]), .I(DATA_OUT[0]), .T(READ_WRITE));
OBUFT_S OUPUT_PATH_1 (.O(DATA[1]), .I(DATA_OUT[1]), .T(READ_WRITE));
endmodule
bnd_scan.v /////////////////////////////////////////////////////
// BND_SCAN.V Version 1.0 //
// Example of instantiating the BSCAN symbol in //
// activating the Boundary Scan circuitry //
// Count4 is an instanited .v file of a counter //
// September 1997 //
/////////////////////////////////////////////////////
module bnd_scan (LOAD_P, CLOCK_P, CE_P, RESET_P,
DATA_P, COUT_P);
input LOAD_P, CLOCK_P, CE_P, RESET_P;
input [3:0] DATA_P;
output [3:0] COUT_P;
wire TDI_NET, TMS_NET, TCK_NE, TDO_NET;
BSCAN U1 (.TDO(TDO_NET), .TDI(TDI_NET), .TMS(TMS_NET), .TCK(TCK_NET));
TDI U2 (.I(TDI_NET));
TCK U3 (.I(TCK_NET));
TMS U4 (.I(TMS_NET));
TDO U5 (.O(TDO_NET));
count4 U6 (.LOAD(LOAD_P), .CLOCK(CLOCK_P), .CE(CE_P),
.RST(RESET_P), .DATA(DATA_P), .COUT(COUT_P));
endmodule
count4.v
/////////////////////////////////////////////////////
// BND_SCAN.V Version 1.0 //
// Example of instantiating the BSCAN symbol in //
// activating the Boundary Scan circuitry //
// Count4 is an instanited .v file of a counter //
// September 1997 //
/////////////////////////////////////////////////////
module bnd_scan (LOAD_P, CLOCK_P, CE_P, RESET_P,
DATA_P, COUT_P);
input LOAD_P, CLOCK_P, CE_P, RESET_P;
input [3:0] DATA_P;
output [3:0] COUT_P;
wire TDI_NET, TMS_NET, TCK_NE, TDO_NET;
BSCAN U1 (.TDO(TDO_NET), .TDI(TDI_NET), .TMS(TMS_NET), .TCK(TCK_NET));
TDI U2 (.I(TDI_NET));
TCK U3 (.I(TCK_NET));
TMS U4 (.I(TMS_NET));
TDO U5 (.O(TDO_NET));
count4 U6 (.LOAD(LOAD_P), .CLOCK(CLOCK_P), .CE(CE_P),
.RST(RESET_P), .DATA(DATA_P), .COUT(COUT_P));
endmodule
|